: Embedded Linux Primer: A Practical, Real-World Approach

D.3. SDRAM Setup

D.3. SDRAM Setup

After the clocks have been configured, the next step is to configure the SDRAM controller. Controllers vary widely from processor to processor, but the end result is always the same: You must provide the correct clocking and timing values to enable and optimize the performance of the SDRAM subsystem.

As with other material in this book, there is no substitute for detailed knowledge of the hardware you are trying to configure. This is especially so for SDRAM. It is beyond the scope of this appendix to explore the design of SDRAM, but some basics must be understood. Many manufacturers' data sheets on SDRAM devices contain helpful technical descriptions. You are urged to familiarize yourself with the content of these data sheets. You don't need a degree in hardware engineering to understand what must be done to properly configure your SDRAM subsystem, but you need to invest in some level of understanding.

Here we examine how the SDRAM controller is configured on the 405GP processor as configured by the U-Boot bootloader we covered in Chapter 7, "Bootloaders." Recall from Chapter 7 that U-Boot provides a hook for SDRAM initialization from the assembly language startup code found in start.S in the 4xx-specific cpu directory. Refer back to Section 7.4.4 "Board-Specific Initialization" in Chapter 7. Listing D-1 reproduces the sdram_init() function from U-Boot's .../cpu/ppc4xx/sdram.c file.

Listing D. ppc4xx sdram_init() from U-Boot

01 void sdram_init(void)
02 {
03 ulong sdtr1;
04 ulong rtr;
05 int i;
07 /*
08 * Support for 100MHz and 133MHz SDRAM
09 */
10 if (get_bus_freq(0) > 100000000) {
11 /*
12 * 133 MHz SDRAM
13 */
14 sdtr1 = 0x01074015;
15 rtr = 0x07f00000;
16 } else {
17 /*
18 * default: 100 MHz SDRAM
19 */
20 sdtr1 = 0x0086400d;
21 rtr = 0x05f00000;
22 }
24 for (i=0; i<N_MB0CF; i++) {
25 /*
26 * Disable memory controller.
27 */
28 mtsdram0(mem_mcopt1, 0x00000000);
30 /*
31 * Set MB0CF for bank 0.
32 */
33 mtsdram0(mem_mb0cf, mb0cf[i].reg);
34 mtsdram0(mem_sdtr1, sdtr1);
35 mtsdram0(mem_rtr, rtr);
37 udelay(200);
39 /*
40 * Set memory controller options reg, MCOPT1.
41 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
42 * read/prefetch.
43 */
44 mtsdram0(mem_mcopt1, 0x80800000);
46 udelay(10000);
48 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
49 /*
50 * OK, size detected -> all done
51 */
52 return;
53 }
54 }

The first action reads the pin strapping on the 405GP processor to determine the design value for the SDRAM clock. In this case, we can see that two possible values are accommodated: 100MHz and 133MHz. Based on this choice, constants are chosen that will be used later in the function to set the appropriate register bits in the SDRAM controller.

Starting on line 24, a loop is used to set the parameters for each of up to five predefined memory sizes. Currently, U-Boot has logic to support a single bank of memory sized at 4MB, 16MB, 32MB, 64MB, or 128MB. These sizes are defined in a table called mb0cf in .../cpu/ppc4xx/sdram.c. The table associates a constant with each of these memory sizes, based on the value required in the 405GP memory bank configuration register. The loop does this:

for (i = each possible memory bank size, largest first) {
select timing constant based on SDRAM clock speed;
disable SDRAM memory controller;
configure bank 0 with size[i], timing constants[i];
re-enable SDRAM memory controller;
run simple memory test to dynamically determine size;
/* This is done using get_ram_size() */
if (tested size == configured size) done;

This simple logic simply plugs in the correct timing constants in the SDRAM controller based on SDRAM clock speed and configured memory bank size from the hard-coded table in U-Boot. Using this explanation, you can easily correlate the bank configuration values using the 405GP reference manual. For a 64MB DRAM size, the memory bank control register is set as follows:

Memory Bank 0 Control Register = 0x000a4001

The PowerPC 405GP User's Manual describes the fields in Table D-2 for the memory bank 0 control register.

Table D-2. 405GP Memory Bank 0-3 Configuration Register Fields

Field Value Comments
Bank Address (BA) 0x00 Starting memory address of this bank.
Size (SZ) 0x4 Size of this memory bankin this case, 64MB.
Addressing Mode (AM) 0x2 Determines the organization of memory, including the number of row and column bits. In this case, Mode 2 = 12 row address bits, and either 9 or 10 column address bits, and up to four internal SDRAM banks. This data is provided in a table in the 405GP user's manual.
Bank Enable (BE) 0x1 Enable bit for the bank configured by this register. There are four of these memory bank configuration registers in the 405GP.

The values in this table must be determined by the designer, based on the choice of memory module in use on the board.

Let's look at a timing example for more detail on the timing requirements of a typical SDRAM controller. Assuming a 100MHz SDRAM clock speed and 64MB memory size, the timing constants selected by the sdram_init() function in Listing D-1 are selected as follows:

SDRAM Timing Register = 0x0086400d
Refresh Timing Register = 0x05f00000

The PowerPC 405GP User's Manual describes the fields in Table D-3 for the SDRAM Timing Register.

Table D-3. 405GP SDRAM Timing Register Fields

Field Value Comments
CAS Latency (CASL) 0x1 SDRAM CAS Latency. This value comes directly from the SDRAM chip specifications. It is the delay in clock cycles required by the chip between issuance of the read command (CAS signal) until the data is available on the data bus. In this case, the 0x1 represents two clock cycles, as seen from the 405GP user's manual.
Precharge Command to Next Activate (PTA) 0x1 The SDRAM Precharge command deactivates a given row. In contrast, the Activate command enables a given row for subsequent access, such as during a burst cycle. This timing parameter enforces the minimum time between Precharge to a subsequent Activate cycle and is dictated by the SDRAM chip. The correct value must be obtained from the SDRAM chip specification. In this case, 0x1 represents two clock cycles, as determined from the 405GP user's manual.
Read/Write to Precharge Command Minimum (CTP) 0x2 This timing parameter enforces the minimum time delay between a given SDRAM read or write command to a subsequent Precharge command. The correct value must be obtained from the SDRAM chip specification. In this case, 0x2 represents three clock cycles, as determined from the 405GP user's manual.
SDRAM Command Leadoff (LDF) 0x1 This timing parameter enforces the minimum time delay between assertion of address or command cycle to bank select cycle. The correct value must be obtained from the SDRAM chip specification. In this case, 0x1 represents two clock cycles, as determined from the 405GP user's manual.

The final timing parameter configured by the U-Boot example in Listing D-1 is the refresh timing register value. This register requires a single field that determines the refresh interval enforced by the SDRAM controller. The field representing the interval is treated as a simple counter running at the SDRAM clock frequency. In the example here, we assumed 100MHz as the SDRAM clock frequency. The value programmed into this register in our example is 0x05f0_0000. From the PowerPC 405GP User's Manual, we determine that this will produce a refresh request every 15.2 microseconds. As with the other timing parameters, this value is dictated by the SDRAM chip specifications.

A typical SDRAM chip requires one refresh cycle for each row. Each row must be refreshed in the minimum time specified by the manufacturer. In the chip referenced in Section D.4.1, "Suggestions for Additional Reading," the manufacturer specifies that 8,192 rows must be refreshed every 64 milliseconds. This requires generating a refresh cycle every 7.8 microseconds to meet the specifications for this particular device.

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